When use mInternalCr3, GetPageTableEntry() get the 5 level paging state by hardware Cr4.Bits.LA57. But it should use the paging level state when create mInternalCr3.
Wei is working on it.
If mInternalCr3 is non zero, it will use the page table from mInternalCr3. And it will use mInternalIs5LevelPaging to reflect the page table type. If use page table from CR3, reflect the page table type by CR4 LA57 bit. PiCpuSmmEntry() will generate the page table of SMM shack memory. If CET feature is enabled, it also includes the SMM shadows shack memory. And we need to set some attributes on SMM shadows shack memory in PiCpuSmmEntry() when CET feature is enabled. Since the page table of SMM shack memory is used in SMI entry, and it does not set to CR3 in PiCpuSmmEntry(). We use mInternalCr3 as page table root when PiCpuSmmEntry() calls ConvertMemoryPageAttributes(). We need to use mInternalIs5LevelPaging determining whether 5-level paging is enabled or not. If mInternalCr3 is zero, ConvertMemoryPageAttributes() will use the page table in CR3, and refects the page table type by CR4 LA57 bit. It is a bug fix when enable CET feature with 5 level paging. https://bugzilla.tianocore.org/show_bug.cgi?id=1521 https://bugzilla.tianocore.org/show_bug.cgi?id=1946
The patch is merged. https://github.com/tianocore/edk2/commit/404250c8f77d09077321766602c3118cec7f6ecd#diff-046f96e518d3e1cc29af30e1e2766e8ccbfaef1465cd8fe7fcc167b1a45fcb02