<Michael.Roth@...> wrote: While at it, could you please fix your email setup and use 8bit transfer encoding instead of quoted printable? Also, please put me on cc so I don't have to

Tom just noticed another spot where a non-leaf C-bit needs to be cleared (the one mapping the GHCB page). It doesn't affect patch functionality but should be included for completeness of this change,

For the most part, OVMF will clear the encryption bit for MMIO regions, but there is currently one known exception during SEC when the APIC base address is accessed via MMIO with the encryption bit

I don't have a lot of experience with SMM. I believe Paolo first ported over the support into OVMF and might have more insight? I'll try to take a look at it when I can, but maybe @Abner or @Abdul

Reviewed-by: Gua Guo <gua.guo@...>

This patch is to remove legacy SmBase relocation in PiSmmCpuDxeSmm Driver. The responsibility for SmBase relocation has been transferred to the SmmRelocationInit interface, which now handles the

This patch just includes SmmRelocationLib in UefiPayloadPkg. Cc: Sean Rhodes <sean@...> Cc: James Lu <james.lu@...> Cc: Gua Guo <gua.guo@...> Cc: Ray Ni

This patch is to consume SmmRelocationInit for SmBase Relocation. Cc: Jiewen Yao <jiewen.yao@...> Cc: Gerd Hoffmann <kraxel@...> Cc: Ray Ni <ray.ni@...> Signed-off-by: Jiaxin Wu

Based on gSmmBaseHobGuid: If gSmmBaseHobGuid found, means SmBase info has been relocated and recorded in the SmBase array. So, this patch check smbase relocation is done or not

This patch refines the SmmAccess implementation: 1. SmramMap will be retrieved from the gEfiSmmSmramMemoryGuid instead of original from the TSEG Memory Base register. 2. Remove the

In the PiSmmCpuDxeSmm driver, SMRAM allocation for SMI handlers and processor Save State areas was traditionally performed using the Smst->AllocatePages() function during the DXE phase. The

There are below 2 differences between AMD & OVMF according existing implementation: 1.The mode of the CPU check is different between the AMD & OVMF. OVMF: CpuSaveState->x86.SMMRevId & 0Xffff AMD:

Due to the definition difference of SMRAM Save State, SmmBase config in SMRAM Save State for AMD is also different. This patch provides the AmdSmmRelocationLib library instance to handle the SMRAM

This patch is to remove unnecessary CpuIndex. Cc: Zeng Star <star.zeng@...> Cc: Gerd Hoffmann <kraxel@...> Cc: Rahul Kumar <rahul1.kumar@...> Signed-off-by: Jiaxin Wu

This patch aims on mProcessorInfo global variable, which can be defined as local variable in SmmRelocateBases(). With this patch, no need to allocate the memory for all CPUs to store the Processor

Since SMM relocation is performed serially for each CPU, there is no need to allocate buffers for all CPUs to store the SmBase address in mSmBase and the Rebased flag in mRebased. A defined global

This patch aims to rename global variables for clearer association with Smm Init, ensuring their names are distinct from those used in the PiSmmCpuDxeSmm Driver. Cc: Zeng Star

This patch just separates the smbase relocation logic from PiSmmCpuDxeSmm driver, and moves to the SmmRelocationInit interface. It maintains the original implementation of most functions and leaves

Intel plans to separate the smbase relocation logic from PiSmmCpuDxeSmm driver, and the related behavior will be moved to the new interface defined by the SmmRelocationLib class. The SmmRelocationLib

PR: https://github.com/tianocore/edk2/pull/5546 Intel plans to separate the smbase relocation logic from PiSmmCpuDxeSmm driver, and the related behavior will be moved to the new interface defined by